Job Details:

Job Description:

• This technical role will see you grow as a Design methodology and Automation Physical Verification (PV) engineer who defines, enables and consults on everything PV on official signoff for tape-out and development work.
• Work with design teams to align on PV methodology, provides technical guidance and support to the design team and stakeholders throughout the design cycle on flows for quality tape-out.
• Liaise with Foundry, EDA vendor’s and DMA teams for enablement, address bugs, enhancement request and establish support when needed.
• Develop effective methods to address PV challenges in regard to process, tools, or flows.
• Works on runset/rule deck development and efficiency enhancements to improve turn-around-time.
• Familiar with backend IC design Tools, Flows and Methodologies and provide best suited coding to achieve intended functional goals.
• Practice sound engineering best practices - unit test, regression, and automation for timely releases.
• Run efficiency study and benchmarking that drive metrics for project review and improvements.

Qualifications:

• Bachelor's/Master’s Degree in Electrical and Electronics Engineering, Computer Engineering, Microelectronics Engineering, or closely related field.
• Proficient or has experience with Calibre and/or ICV runset development.
• Having methodology knowledge in ERC, RC extraction, RV, HV is an added advantage.
• Knowledge in tcl, shell, perl, python scripting, or has interest in Machine Learning and Artificial Intelligence will be an added advantage.
• Able to communicate well, willing to learn and grow as part of an amazing team.

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